1. Technical Field
The present invention relates to a semiconductor memory apparatus, and more particularly, to a pipe register circuit capable of improving an operation speed and a semiconductor memory apparatus having the same.
2. Related Art
In general, in a semiconductor memory apparatus such as a dynamic random access memory (DRAM), data stored in a cell is read through a data output circuit. When the stored data is read, the data is output after being delayed by a predetermined number of clocks from a clock, on which a read command is input, by CAS latency CL according to JEDEC specifications.
FIG. 1 is a block diagram illustrating a part of a general semiconductor memory apparatus, and FIG. 2 is a timing diagram for explaining a data read operation of the general semiconductor memory apparatus.
Referring to FIG. 1, the general semiconductor memory apparatus includes a cell array 10, an address buffer 20, an address latch 30, a command buffer 40, a data pipe register 50, an output enable control unit 60, and an output driver 70.
The operation of the semiconductor memory apparatus having the configuration will be described with reference to FIG. 2. In the general semiconductor memory apparatus, when a read command is input from an external, the input read command is input to the command buffer 40. When the read command is output from the command buffer 40 in synchronization with a clock, a corresponding address signals address, which has been latched in the address latch 30 after being input together with the read command, is output.
Data stored in a corresponding cell of the cell array 10 is read by the output address signals address, and is temporarily stored in the data pipe register 50. There is a delay, noted by delay A, when the read command is input from an external and the read data is stored in the data pipe register 50.
Then, the read data stored in the data pipe register 50 is transferred to a global input/output line GIO in response to an output control signal out_ctrl output from the output enable control unit 60 in correspondence with CAS latency CL, and then is output to an external through the output driver 70. There is a delay, noted by delay B, when the read command is output from the data pipe register 50 and then is output through the output driver 70.
The general semiconductor memory apparatus configured as above includes the data pipe register 50 for each data input/output pad (not illustrated). When the number of data input/output pads is large, the data pipe register 50 is provided by the number of data input/output pads, resulting in an increase in the area of the semiconductor memory apparatus.
Furthermore, in the general semiconductor memory apparatus configured as above, there is delay, notably delay A and delay B, from when the read command is input to when the read data is output to an external, resulting in a reduction of the operation speed of the semiconductor memory apparatus.